1. Technical Field
Embodiments of the inventive concepts relate generally to semiconductor integrated circuits, and more particularly to non-volatile memory devices and methods of operating non-volatile memory devices.
2. Discussion of the Related Art
Semiconductor memory devices may generally be classified as volatile memory devices or non-volatile memory devices depending on whether the data stored therein is maintained when power is not supplied to the device. Non-volatile memory devices may include electrically erasable and programmable ROM (EEPROM) devices.
EEPROM devices may be operated in a program mode for writing data in memory cells, a read mode for reading out the data stored in the memory cells or an erase mode for initializing the memory cells by deleting the data stored therein. In incremental step pulse programming (ISPP), programming and verification steps may be repeated until the verification is successful.
Non-volatile memory devices may be implemented as single-level cells (SLC) or multi-level cells (MLC). A SLC may store a single data bit, while MLCs may store two or more bits per cell. The distribution of threshold voltages of an SLC may be divided into two states, which may be represented as ‘1’ and ‘0’ in an order of increasing threshold voltage distributions. In this case, ‘1’ corresponds to an erase state having the lowest threshold voltage distribution of the memory cells that are not programmed.
In contrast, a multi-level cell (MLC) may store at least two data bits. When N bits are stored in an MLC, the distribution of the threshold voltages of the MLCs may be divided into 2N states, with each state representing a corresponding value of the N-bit data. For example, when two bits are stored in each MLC, the distribution of the threshold voltages may be divided into four states, which may be represented as ‘11’, ‘10’, ‘01’ and ‘00’ in an order of the increasing threshold voltages. In this case, ‘11’ corresponds to an erase state having the lowest threshold voltage distribution of the memory cells that are not programmed.
The data retention capability of the memory cells in the programmed state may be degraded due to an erase-to-program interval (EPI) effect caused by the memory cells in the erased state.